Simulation - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

The Wizard example design test bench can be simulated to quickly demonstrate core and transceiver functionality. For more information, see Test Bench.

For comprehensive information about Vivado® simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900).

See the Vivado Design Suite Tutorial: Logic Simulation (UG937) for additional references of using xil_dut_bypass module, for automated hierarchical reference port access in PAM4 Signal Inference in GTM Transceivers top for simulation.

Note: Powerdown operation is not modeled in simulation