Simulation Behavior - 1.0 English

The example design simulation test bench provides the requisite free-running clock and transceiver reference clock signals, as well as a “reset all” pulse to the example design logic and reset controller helper block input ports. This stimulus is sufficient to allow the helper blocks to bring up the remainder of the system. After some time, the transceiver PLL(s) will achieve lock, allowing the reset controller helper block finite state machines to complete the full reset sequence. After the reset sequence is complete, you can begin to observe the example stimulus module transmitting data. A short time later, the example checking module begins to search for data alignment and checks for data integrity, which is in turn used by the link status logic to drive the link status indicator.

Note: To quickly demonstrate operation of the entire example design, the simulation test bench asserts “reset all” from the beginning of operation.

The example design output port link_status_out indicates a PRBS match-based link across all channels. The test bench uses a counter to detect a level link_status_out assertion, and deassertions reset the counter. When the counter saturates, the test bench prints this message to the transcript:

Initial link achieved across all transceiver channels.

The test bench then pulses link_down_latched_reset_in to reset the example design sticky link down indicator, and allows the simulation to run for a prescribed period of time to ensure that the link is maintained. These messages are printed to the transcript:

Resetting latched link down indicator.
Continuing simulation for 50us to check for maintenance of link.

At the end of the prescribed wait period, the test bench checks whether the link has been maintained. If so, the following messages are printed to the transcript and the test is considered to have passed.

The simulation then finishes: PASS: simulation completed with maintained link.
 ** Test completed successfully.

The following figure shows the characteristic waveform of a passing test, demonstrating initial link, a saturating link up counter leading to the link stable indicator, a pulse to reset the sticky link down indicator, and the beginning of the wait period where the test bench is run while the sticky link down indicator remains deasserted. The signals shown are those from the test bench level of hierarchy only, and are the default set when loading a simulation from the Vivado® design tools. You might wish to add additional signals to the waveform window for more visibility into the operation of the example design or the core instance.

Figure 1. Test Bench Simulation Waveform of a Passing Test

If the link is lost after it was first achieved, the following messages are printed to the transcript and the test is considered to have failed. The simulation then finishes:

FAIL: simulation completed with subsequent link loss after initial link.
** Error: Test did not complete successfully

Use the “run all” feature of your simulator to allow the simulation to run for an unbounded period of time. The provided test bench includes a timeout process that, should the time limit be reached before a stable link is first achieved, prints the following message to the transcript before exiting the simulation. This behavior is considered a test failure and is not expected:

FAIL: simulation timeout. Link never achieved.
** Error: Test did not complete successfully