The supported operating sub-modes for 100GE and 50GE are summarized in the following table. In all modes where virtual lane alignment markers and frame lengths are defined, these are configurable via core parameters. Some restrictions are imposed by the FEC layer, for example, frame length must be such that the alignment markers always fall at the start of a FEC codeword. This means that in 100GE mode, the length should be a multiple of 4, and in 50GE mode, the length should be a multiple of 20. A full set of status flags is provided by the RS-FEC block to enable the erroring of 66b sync headers by the RX transcoder in the case of an uncorrected codeword.
| Rate | Indication Bypass | Correction Bypass | Indication and Correction Bypass |
|---|---|---|---|
| 100G | Full support as per standard | Full support as per standard | Full support (although not required by standard) |
| 50G | Full support as per standard | Full support as per standard | Full support (although not required by standard) |
The nominal operating mode against standard line rates is given in the following table. However, the GTM Wizard IP GUI provides the option to modify the line rates for over/under sampling modes. If this option is selected, ensure the standard ratio of GTM clock to MAC clock rates are matched as shown in the following table. To illustrate this, the GTM Wizard IP example design instantiates a clocking wizard block for reference.
| FEC Mode | Nominal SERDES Clock Rate (MHz) | Nominal MAC Clock Rate (MHz) |
|---|---|---|
| 100GE KP4 (53.125 Gb/s X2) | 332.03125 | 322.265625 |
| 50GE KP4(53.125 Gb/s X1) | 332.03125 | 390.625 |
N PCS lanes are multiplexed to form the data stream that is fed in to the Transcoder, where N=20 in a 100GE system and N=4 in a 50GE system. Each PCS lane contains an alignment marker once in every FEC_VL_LENGTH 66b blocks. This is because the PCS layer processes 66b blocks of data. The units used to specify GUI input for FEC_VL_LENGTH_CWS and FEC_VL_LENGTH_CWS_RX is the number of codewords - whose typical configuration values are 4096@100GE and 1024@50GE.
The functionality and high-level architecture required for the soft Ethernet transcoding IP block is described in the following figures. The functions managed in the Transcode block include Lane Block Lock, Alignment Lock, Alignment Marker Removal, 64b/66b to 256b/257b Transcoding, and related Alignment marker mapping and insertion. The Transcoding logic helper block has a fixed, deterministic latency, excluding the latency of the CDC crossing FIFO.
