The transmitter user clocking network helper block is a simple module used to derive and
buffer the appropriate clocks to drive the TXUSRCLK and
TXUSRCLK2 inputs of one or more transceiver channels.
A single instance of the helper block is delivered with each instance of
the Wizard IP core. By default, its source clock input port, gtwiz_userclk_tx_srcclk_in, is driven by the TXOUTCLK port of the master transceiver channel. Within the helper block, this
source drives either one or two BUFG_GT primitives, which are global clock buffers that are
capable of clock division.
As shown in the following figure, if the TXUSRCLK and
TXUSRCLK2 frequencies are identical (which is the case when the
transmitter user data width is narrower than or equal to the size of the internal data
width), then only a single BUFG_GT is instantiated within the helper block. This buffer
drives both gtwiz_userclk_tx_usrclk_out and
gtwiz_userclk_tx_usrclk2_out helper block output ports, which are wired
to the TXUSRCLK and TXUSRCLK2 input ports, respectively,
of each transceiver channel primitive. The helper block configures the BUFG_GT to divide the
source clock down to the correct user clock frequency as required.
As shown in the above figure, if TXUSRCLK is twice the frequency of
TXUSRCLK2 (which is the case when the transmitter user data width is
wider than the internal data width), then two BUFG_GT primitives are instantiated within the
helper block. The helper block configures one BUFG_GT to divide the source clock down to the
correct transmitter datapath frequency and drive the
gtwiz_userclk_tx_usrclk_out helper block output port, which is wired to
the TXUSRCLK input port of each transceiver channel. The helper block
configures the other BUFG_GT to divide the source clock down to the correct transmitter user
interface frequency and drive the gtwiz_userclk_tx_usrclk2_out helper block
output port, which is wired to the TXUSRCLK2 input port of each transceiver
channel.
The helper block holds BUFG_GT primitive(s) in reset when the
gtwiz_userclk_tx_reset_in user input is asserted. This reset input should
be held High until the source clock input is known to be stable. When the reset input is
released, the gtwiz_userclk_tx_active_out user indicator synchronously
asserts, indicating an active user clock and allowing dependent helper blocks to proceed.
The helper block can be located either within the core, or in the example design, per user
selection. If included within the core, wiring from the master transceiver channel
TXOUTCLK output port to the helper block
gtwiz_userclk_tx_srcclk_in input port is also internal to the core, but
that clock signal is presented on the core interface as
gtwiz_userclk_tx_srcclk_out. Similarly, wiring between the helper block
gtwiz_userclk_tx_usrclk_out and
gtwiz_userclk_tx_usrclk2_out output ports and the transceiver channel is
internal to the core but those helper block outputs are also presented on the core
interface.
If the helper block is located within the example design, then by necessity the relevant transceiver channel clock ports are enabled on the core interface so that the necessary signals can cross the core boundary.
For complete documentation on clocking the transceiver primitives, see Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581).