Basic Tab - 1.0 English

Basic tab is shown in the following figure:

Figure 1. Basic Tab

See Customizing and Generating the Core for more information.

Component Name

Component name is user defined. Component names must not contain any reserved words in Verilog.

Application

Source Synchronous: Indicates that the data capture clock is present along with the data on the serial lines.

Asynchronous: Indicates that there is no data capture clock on the serial lines for RX buses.

Bus Direction

Indicates the direction of the pins in the user design

TX ONLY: Indicates that the user design contains only TX pins.
RX ONLY: Indicates that the user design contains only RX pins.
TX +RX: Indicates that the user design contains TX and RX pins.
BiDir: Indicates that the user design contains BiDir Pins.
BiDir+Tx_Rx: Indicates that the user design contains a mix of TX, RX and BiDir pins.

Clocking

Enable Zero PPM CDR (Beta)

Enable this option to use CDR with Zero PPM mode. CDR with PPM difference mode is used by default when the application is set to asynchronous mode.

Enable Zero PPM IO Type

When Enable Zero PPM CDR option is selected, both single-ended and differential IOs are supported. However, in a design, either single-ended or differential IO is supported at a time but not both.

Interface Speed (Mb/s):

Sets the interface speed for the configuration. The interface speed has different limits, defined by the device and the selected speed grade. For more information, see Versal Architecture and Product Data Sheet: Overview (DS950).

PLL Clock Source

The clock is sent to the XPLL through the buffer set in this option.

Clock Capable Pin: Choose this option if the input clock is available on the GC pin. In this case the input clock goes to XPLL via IBUF (for single-ended clock) or IBUFDS (for differential clock) instantiated by the wizard.
Fabric (Driven by BUFG): Choose this option if the clock is sent from the general interconnect. The wizard connects the input clock port (clk) directly to the XPLL. You need to ensure that a BUFG is instantiated in the interconnect.

PLL Driven by Data Capture Clock

This option describes the input clock connection to XPLL. If it is chosen as "Yes", then STROBE that is selected from "STROBE SELECTION" in Pin Configuration tab will be connected to XPLL input and also to XPHY.

XPLL Input Clk Frequency (MHz): Sets the input clock frequency for the XPLL. Depending on the data speed selected, a range of supported input clock frequencies are listed.

Forwarded Clock Phase (Tx Signal Type = Clk Fwd): Available only for the TX pins. Sets the phase between clock forward and TX data. Supported values are 0 and 90.

Clock Data Relation (RX Strobe)

Indicates the alignment of external clock to data. This is applicable for RX and BiDir pins.

ASYNC/NONE: Refer to Clocking section for detailed information.
Center DDR: Applicable to RX pins. Refer to Clocking in Chapter 4 for detailed information.
EDGE DDR: Applicable to RX pins. Refer to Clocking in Chapter 4 for detailed information.

Data and Control

Enable Custom CDR

You can have your own custom CDR block independently for asynchronous RX applications.

TX/RX Serialization Factor

Defines the serialization factor for parallel data input/output width from/to the general interconnect. Legal values are 2, 4, and 8. The serialization factor is set to 8 by default. These parameters are disabled when Bus Direction is BiDir/BiDir+RX+TX.

Serialization Factor

Application Data Width

Defines the serialization factor for parallel data input/output width from/to the general interconnect in the case of Async Mode.

3-State

Sets the tristate control for TX pins.

3-State

Combinatorial: Uses the T pin of the XPHY. The T input from the general interconnect logic directly goes to XPHY nibble which controls the 3-state of the TX and BiDir pins.
Serialized: PHY_WREN port is used to 3-state the TX and BiDir pins.

Enable Bitslip

For bus direction RX, and BiDir bitslip logic can be enabled to byte alignment. This option is not available for Serialization factor 2.

Enable Data Bitslip

Enables the XPHY RX output to be presented, even before the bitslip is completed.

Bitslip Training Pattern

For Bitslip logic to achieve sync, a pre-defined training pattern (in HEX format) should be received. The training pattern should be unique and defined by the higher level protocol. The start_bitslip port (active-Low) holds the bitslip logic in reset. The start_bitslip port should be driven High only when the transmitter has started driving the valid bitslip training pattern. The transmitter is expected to send the training pattern continuously until the bitslip_sync_done is asserted.

Note: Bitslip Detector cannot detect continuous 1's or 0's. So avoid "F" and "0" in any nibble of the Bitslip pattern.

Enable RIU Interface

Enables Register Interface Unit (RIU) for all nibbles to access internal registers. Every delay element tap setting can be read with the RIU. Various features, such as clock gating and Voltage Temperature tracking, can be disabled. It enables the RIU access, but does not add additional logic for RIU access.

Include PLL In Core

Enabling this option includes XPLL inside the core. It generates all the clocks required by the user. Number of XPLLs are instantiated based on the Number of banks requested.