The Advanced IO Wizard core provides the source HDL wrapper for the high performance XPHY nibble primitives. It also generates optimum pin placement for the user-defined interface pins.
The wizard configures bus direction, clock to data alignment, interface speed, XPLL clock source, XPLL input clock frequency, IO standard and DC bias selection for the interface. The wizard builds a complex high speed I/O interface through XPHY parameter settings, clock setup, clock routing, and forwarding that allows simple I/O user input for complex applications. Additionally, bitslip can be enabled for RX/BiDir pins.
The wizard also configures pin/bus selection, bus direction, signal type,
data/strobe, and signal name. It allows you to choose the TX/RX/BiDir bus direction for
the signals in the interface. Each IO bank contains 54 pins that can be configured as
TX/RX/BiDir. The wizard provides the following features:
- TX/RX/BiDir
- Single ended/Differential
- Data/Strobe/Input clock/Clock forward/WrClk/RdClk
- Customizable bus signal name