Next, create constant IPs, and connect them using Tcl commands. A block diagram shows the results.
Note: Because the tutorial is
focused on the Receive interface and Clocking Wizard, individual instructions to step through the Constant
IPs and connectivity are not provided.
The Tcl commands used to create the Constant IP and connect the IPs are as follows:
#make the parallel data a device output
make_bd_pins_external \
[get_bd_pins advanced_io_wizard_0/data_to_fabric_dataIn]
set_property name parallel_dataOut [get_bd_ports data_to_fabric_dataIn_0]
#create single bit logic 1 constant and connect
create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1
connect_bd_net [get_bd_pins advanced_io_wizard_0/en_vtc] \
[get_bd_pins xlconstant_1/dout]
#create multi-bit constant and connect
create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2
set_property -dict [list CONFIG.CONST_WIDTH {9}] \
[get_bd_cells xlconstant_2]
connect_bd_net [get_bd_pins xlconstant_2/dout] \
[get_bd_pins advanced_io_wizard_0/fifo_rd_en]
#connect clocks
make_bd_pins_external [get_bd_pins clk_wizard_0/clockIn]
connect_bd_net [get_bd_pins clk_wizard_0/refClk] \
[get_bd_pins advanced_io_wizard_0/ctrl_clk]
connect_bd_net [get_bd_pins clk_wizard_0/refClk] \
[get_bd_pins advanced_io_wizard_0/bank0_pll_clkin]
connect_bd_net [get_bd_pins advanced_io_wizard_0/bank0_pll_clkout0] \
[get_bd_pins advanced_io_wizard_0/fifo_rd_clk]
#create and connect ports
make_bd_pins_external [get_bd_pins advanced_io_wizard_0/rst]
set_property name rst [get_bd_ports rst_0]
make_bd_pins_external [get_bd_pins advanced_io_wizard_0/bank0_pll_rst_pll]
set_property name rst_pll [get_bd_ports bank0_pll_rst_pll_0]
make_bd_pins_external [get_bd_pins advanced_io_wizard_0/intf_rdy]
make_bd_pins_external [get_bd_pins advanced_io_wizard_0/dataIn]
make_bd_pins_external [get_bd_pins advanced_io_wizard_0/strbClk]The resulting block diagram is as follows:
Figure 1. Final Block Diagram
