Create and Configure the Clocking Wizard IP - 1.0 English

Advanced IO Wizard LogiCORE IP Product Guide (PG320)

Document ID
PG320
Release Date
2022-10-19
Version
1.0 English

Next, create and configure the Clocking Wizard IP for the 300 MHz reference clock.

  1. In the block design canvas, click Add IP.
  2. In the popup, search for Clocking Wizard and double-click Clocking Wizard to add it to the canvas.
  3. On the canvas, double-click the Clocking Wizard to step through IP configuration:
    1. In the Clocking Features tab, set:
      • Input Clock Information: For Primary Input Clock, enter Port Name clockIn, and set Input Frequency to 125.00 MHz.
    2. In the Output Clocks tab, set:
      • For Output Clock clk_out1, enter Port Name refClk, and set Output Frequency Requested to 300.00 MHz.
      • Click on Calculate Actual Values to update the Output Frequency Actual
    3. Use the defaults available in MMCM Settings and Optional Port tabs.

The Tcl commands used to create and configure the Clocking Wizard are as follows:

create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wizard:1.0 clk_wizard_0

set_property -dict [list CONFIG.PRIM_IN_FREQ.VALUE_SRC USER] \
                         [get_bd_cells clk_wizard_0]

set_property -dict [list CONFIG.PRIM_IN_FREQ {125.000} \
  CONFIG.PRIMARY_PORT {clockIn} \
  CONFIG.CLKOUT_USED {true,false,false,false,false,false,false} \
  CONFIG.CLKOUT_PORT \
    {refClk,clk_out2,clk_out3,clk_out4,clk_out5,clk_out6,clk_out7} \
  CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY \
    {300.000,100.000,100.000,100.000,100.000,100.000,100.000} \
  CONFIG.CLKOUT_REQUESTED_PHASE \
    {0.000,0.000,0.000,0.000,0.000,0.000,0.000} \
  CONFIG.CLKOUT_REQUESTED_DUTY_CYCLE \
    {50.000,50.000,50.000,50.000,50.000,50.000,50.000} \
  CONFIG.CLKOUT_DRIVES {BUFG,BUFG,BUFG,BUFG,BUFG,BUFG,BUFG} \
    CONFIG.CLKOUT_DYN_PS {None,None,None,None,None,None,None} \
  CONFIG.CLKOUT_MATCHED_ROUTING \
    {false,false,false,false,false,false,false} \
  CONFIG.CLKFBOUT_MULT {24.000000} \
  CONFIG.CLKOUT1_DIVIDE {10.000000}] \
  [get_bd_cells clk_wizard_0]