This appendix includes details about resources available on the Xilinx Support website and debugging tools.
Steps to insert ILA into a design which includes Advanced IO Wizard:
Advanced IO Wizard is a special core as it involves regenerating of the core post synthesis to support dynamic change of IO LOCs. As this happens post synthesis, the debug_probes added before opt_design will not be valid. So, to support this flow, there are a sequence of steps that must be followed instead of normal synthesis and implementation flow.
On a Vivado design execute the following steps:
- Run synthesis
- Open synthesized design
- Add the new IO LOC XDCs if needed
- Run opt_design
- write_checkpoint post_opt.dcp
- open_checkpoint ./post_opt.dcp
- All the below steps must be executed in the dcp only
- Create ILA core and add dbg signals
- write_checkpoint ./*post_opt.dcp -force
- implement_debug_core
- place_design
- phys_opt_design
- route_design
- write_device_image -file <file_name>.pdi