Design Description - 1.0 English

Advanced IO Wizard LogiCORE IP Product Guide (PG320)

Document ID
PG320
Release Date
2022-10-19
Version
1.0 English

The tutorial design consists of a 12-bit single ended receive interface running at 600 Mb/s with a 300 MHz reference clock, and a strobe signal to capture DDR source-synchronous edge-aligned data from the I/O using the SSTL12 IOSTANDARD. The high-speed I/O data is then de-serialized into 8 bits (1:8) and passed through the built-in FIFO provided in the I/O hardware.

The Versal architecture design solution constructed in this tutorial, project_Versal.xpr, is provided as a design file. The project_Versal.xpr design file contains a Versal architecture XPHY logic interface created using the Vivado IP integrator, the Advanced IO Wizard, and the Advanced I/O Planner in the Vivado® Design Suite 2022.1.

You can download the reference design files from the Xilinx website. Download the file, and extract the ZIP file contents of the design. Open the design in the Vivado tool version specified above.

Note: This tutorial focuses on architectural features, design, design migration, and implementation. This tutorial does not support simulation.