This chapter includes guidelines and additional information to facilitate designing with the core.
General Design Guidelines
This Advanced IO Wizard core is for high-speed Versal® architecture designs and can be configured over wide range of Interface speeds for Source sync and Async configurations.
Refer to the Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956) and Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957) for supported frequencies in Source synchronous Interfaces.
You are expected to have the interface requirements of your application before generating the Advanced IO Wizard specific to your designs — details such as interface speed, clock to data relationship, and system clocking structure. For example, what the source of the XPLL input clock should be.
Once the wizard generates the HDL wrapper, you should run synthesis and perform pin planning using the Advanced I/O Planner tools. For more information, see I/O Planning for Versal Advanced IO Wizard section.