Edge DDR - 1.0 English

Advanced IO Wizard LogiCORE IP Product Guide (PG320)

Document ID
PG320
Release Date
2022-10-19
Version
1.0 English

In this mode, the RX data is captured using the incoming strobe. The strobe input is present on the pin 0 of a XPHY nibble present in a bank. The wizard supports up to eight strobes in a given bank. The propagation of strobes to RX data pins follows the inter-byte and inter-nibble clocking rules as mentioned in the Clocking section of the Versal ACAP SelectIO Resources Architecture Manual (AM010).

The strobe pin nearest to an RX data pin is chosen as the associated strobe for the data pin. Special care needs to be taken while pin planning to ensure that the appropriate strobe and data pin positions are chosen. By default, the wizard chooses an ideal location for the clocks, which Xilinx recommends to use the default configuration.

Figure 1. Edge DDR