This chapter contains information about the example design provided in the Vivado® Design Suite.
This core provides an example design with one core instance and one example
instance. If generating a TX IP instance as an example design, an RX IP is created as part of
the example design for as I/O loopback. Similarly if this is an RX IP instance, a TX IP is
created and looped back by the example design. When bitslip is enabled, the pre-defined
training pattern is compared to align the data at RX. When data is aligned, PRBS patterns are
transmitted from TX and PRBS checkers at the Rx (in the example instance) check for data
integrity. When bitslip is not enabled, data from RX nibbleslices are unaligned data, and the
example design checks for all possible valid data of RX for a known TX data pattern. If a
pattern matches, data_check_complete output is asserted from
the example design.
