- Supports source synchronous and asynchronous I/O interfaces using high performance XPHY primitives.
- Supports user selectable interface types such as TX, RX, BIDIR or a mix of all bus directions.
- Provides Advanced TCL mode for customization features that are not found in wizard GUI, and allows overriding of all SelectIO supported attributes of XPHY.
- For RX and BiDir interface, the clock/strobe to data relationship is selectable based on the protocol setting.
- Serialization factor of 8-bit, 4-bit, and 2-bit is supported.
- Range of the user selectable XPLL input clock frequencies for a given data speed.
- Optional register interface unit (RIU) interface and bitslip logic.
- Provides optimized pin planning solution through automation with pins grouped into pre-defined sets, and can customize after autoplace for specific pin locations.