IP Facts - 1.0 English

Advanced IO Wizard LogiCORE IP Product Guide (PG320)

Document ID
PG320
Release Date
2022-10-19
Version
1.0 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 Versal® ACAP
Supported User Interfaces RIU
Provided with Core
Design Files RTL
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx® Design Constraints (XDC)
Simulation Model Yes
Supported S/W Driver 2 N/A
Tested Design Flows 2
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 76554
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.