This appendix includes details about how a UltraScale™ and UltraScale+™ IO designs can be updated to Versal® IO designs.
- Versal ACAP Design Guide (UG1273) has a table that explains the IO map between the different generations.
- High Speed SelectIO (HSSIO) Wizard that supports UltraScale and UltraScale+ IO designs cannot directly be upgraded toVersal designs. If you have an existing HSSIO Wizard, it is not possible to import the .XCI into Versal.
- You must build the Versal design from scratch, and you must include the CIPS IP along with the other IPs, that are required for the design.
- You can use the Advanced IO Wizard for Source Synchronous or Asynchronous interfaces.
- The Advanced IO Wizard Basic Tab is very similar to the HSSIO Wizard Basic tab. You can map the required options accordingly.
- In the Versal families, the Pin Placement is not done during the Wizard creation. Hence, you must select the number of data channels, the strobe associated and if the channels are single-ended or differential on the Pin Configuration Tab.
- The Pin Planning is then done, either in the Elaborated or Synthesized Design using the Advanced IO Planner in Pin Planning.
- The IO Timing Estimation Tab helps you get the timing estimates of the design. For Source Synch interfaces, the BISC does the data to clock alignment. The Wizard allows you to plug in the information about the board to understand if you have sufficient budget for the interface just utilizing the BISC function.
- Summary Tab lists the groups of the Interfaces requested in the list of tabs in Advanced IO Wizard.