For details, see the Vivado Design Suite User Guide: Designing with IP (UG896).
The wizard delivers Verilog RTL for the core logic, example design, and example test bench.
If the IP example design project is opened, another core instance with the core name <ip_ex_inst> is instantiated in the <ComponentName>_exdes.v. For example design simulation, the <ComponentName>_tb.v test bench file is generated.