PLL Data Capture Clock - 1.0 English

The option of PLL Data Capture clock is available to you only when the CLOCK_SOURCE is selected as Clock Capable Pin (IBUF_TO_PLL).

If you select PLL driven by Data Capture Clock as Yes, it means you have requested the IP to connect to the same strobe (that you have selected) signal to XPLL input and to XPHY.

For BIDIR only and TX Modes, this feature is not be supported as strobe and it is specific to RX.

In the case of selection of this feature, PLL Input clock Frequency (which must be connected to the XPLL input) is automatically updated based on interface speed.

For example, when you select multiple rows, strobes, and features. The IP ask you to select the strobe that must be connected to the XPLL input with the user parameter as STROBE_SEL (Strobe Selection for PLL Input) present in Pin configuration tab.

STROBE_SEL is the drop-down list that contains all the active strobes that can be connected to PLL Input. You can select a strobe from this list.

Placement of the STROBE_SEL (selected strobe) is taken care of and it must be placed in the GC pin location.

In the case of multiple bank design (3 bank design), the selected strobe must be placed in the Scenter bank of three banks so that the adjacent XPLL can be reachable and will give the optimal placement without any issues.

For example, in the above figure, if you select five rows with one row's Pin Direction selected as “None”, all the active (RX Direction) strobes will be displayed in drop-down list for selecting STROBE_SEL.

For example, if you select BUS4_STROBE, the placement/schematic will be as below:

IP ensures that Strobe_4 which you have selected is connected to both XPHY and XPLL input as depicted in the above schematic.