The simple design targeting the xcvc1902-vsvd1760-1LP-e-S device consists of a 12-bit receive interface with a strobe in IOBANK 705 (CLOCK_REGION X5Y0). The de-serialized data from the 12-bit receive interface results in a 96-bit bus that is transmitted out of the device. The Clocking Wizard IP is used to generate the 300 MHz reference clock for the Advanced IO Wizard IP from a 125 MHz input clock using an MMCM. The Advanced IO Wizard IP generates the 75 MHz fabric clock using an XPLL.
Each Versal® device XPHY cell corresponds to six single-ended PACKAGE_PINS/IOBs (or three differential PACKAGE_PINS/IOBs). The 12-bit receive interface requires 12 PACKAGE_PINs, plus an additional PACKAGE_PIN for the single-ended strobe. That means the 12-bit interface requires three XPHY cells. There will be five unused PACKAGE_PINs within the three XPHY cells. The remaining unused PACKAGE_PINs in XPHY logic interfaces can still be used for low-performance I/O logic or as a route-through path to fabric. Refer to XP IOL section of Versal ACAP SelectIO Resources Architecture Manual (AM010) to get more information of using the pins as route through.