About the Core - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

This chapter introduces the Clocking Wizard core and provides related information, recommended design experience, additional resources, technical support, and ways of submitting feedback to Xilinx. The Clocking Wizard core generates source register transfer level (RTL) code to implement a clocking network matched to your requirements. Both Verilog and VHDL design instantiation templates are supported.

The Clocking Wizard core is a Xilinx® IP core that can be generated using the Xilinx Vivado® design tools, included with the latest Vivado Design Suite release in the Xilinx Download Center. The core is licensed under the terms of the Xilinx End User License and no FLEX license key is required.