Auto Buffer Selection and Clock Grouping - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English
  • In auto mode (the clock out drives set to "Buffer"), all those clock outs must be driven through one of the buffers (the buffer can be BUFG or MBUFGCE).
  • In auto mode (the clock out drives set to "Buffer with CE"), all the clock outs are driven through one of the buffers with CE input (BUFGCE or MBUFGCE).
  • IP consider all the clock outs where drives selected as "Buffer" or "Buffer with CE" into auto buffer criteria and which buffer driven through is chosen optimally based on other settings provided by you.
  • MBUFGCE will be inferred if the clock outs are having frequencies as /1, /2 ,/4 and /8 in addition to phase set to 0 degree and duty cycle set to 50% and all those clock out to be under same clock group.
  • Each clock out are provided with five clock group options to choose from
    • Auto- Default option
    • CLOCK_A
    • CLOCK_B
    • CLOCK_C
    • None
  • Auto clock grouping means you do not want to provide any clock grouping explicitly, but IP will make the clocks in to separate groups optimally depending on the MBUFGCE inference
  • At max three MBUFGCE be inferred as auto buffer (as at max seven clocks are present, each MBUFGCE inference to have at least two clocks)
  • For all the clocks selected with explicit clock grouping irrespective of auto buffer selection will be grouped together and the constraints gets generated (CLOCK_DELAY_GROUP constraints will be generated in <ip>.xdc file)

    Following are the example combinations with auto buffer (drives selected as "Buffer") and auto clock grouping:

    1. When all the frequencies are independent to each other (no integer division between any of them) then all clock out are inferred with separate BUFG.
    2. When all the frequencies are integer divides of clk_out1 as in following table
      Table 1. Frequencies with Integer Divides of clk_out1
      Clk_out DIV
      Clk_out1 1
      Clk_out2 2
      Clk_out3 3
      Clk_out4 4
      Clk_out5 5
      Clk_out6 6
      Clk_out7 8
      • Two MBUFGCEs (MBUFGCE1: clkout1,2,4,7 and MBUFGCE2: clkout3,6) and remaining clock (clkout6) with separate BUFG
      • clk1_clr_n is available as clk_out1 is the input to MBUFGCE1 and clk3_clr_n also available as clk_out3 is the input to MBUFGCE2
    3. When some of the frequencies are same as clk_out1 and some are integer divides of clk_out1
      Table 2. Frequencies with same as clk_out1 and Integer Divides of clk_out1
      Clk_out DIV
      Clk_out1 1
      Clk_out2 1
      Clk_out3 1
      Clk_out4 1
      Clk_out5 2
      Clk_out6 3
      Clk_out7 4
      • Three clocks (clkout1,5,7) can be derived from one MBUFGCE and remaining clocks (clkout2,3,4,6) are derived from separate BUFG.
      • clk1_clr_n is available as clk_out1 is the input to MBUFGCE.
    4. When only four clock outs are present and all are integer divides of clk_out1
      Table 3. Four Clocks with /1, /2, /4 and /8 of clk_out1
      Clk_out DIV
      Clk_out1 1
      Clk_out2 2
      Clk_out3 4
      Clk_out4 8
      • MMCM primitive should not be inferred in this case and IP infer MBUFGCE
      • clk1_clr_n is available as clk_out1 is the input to MBUFGCE
    5. When the frequencies are divided by 1 or 2
      Table 4. Frequencies with /1 and /2 of clk_out1
      Clk_out DIV
      Clk_out1 1
      Clk_out2 2
      Clk_out3 1
      Clk_out4 2
      Clk_out5 1
      Clk_out6 2
      Clk_out7 1
      • Three MBUFGCEs (MBUFGCE1: clkout1,2; MBUFGCE2: clkout3,4 and MBUFGCE3: clkout5,6) and remaining clock (clkout7) is inferred through BUFG
      • clk1_clr_n is available as clk_out1 is the input to MBUFGCE1, clk3_clr_n is available as clk_out3 is the input to MBUFGCE2 and clk5_clr_n is available as clk_out5 is the input to MBUFGCE3
    6. When all the frequencies are even integer divides of clk_out1
      Table 5. Frequencies with even Integer Divides of clk_out1
      Clk_out DIV
      Clk_out1 1
      Clk_out2 2
      Clk_out3 2
      Clk_out4 4
      Clk_out5 4
      Clk_out6 6
      Clk_out7 8
      • Two MBUFGCE (MBUFGCE1: clkout1,2,4,7 and MBUFGCE2: clkout3,5) should be used to infer 6 clock outs and remaining clock (clkout6) should be inferred from BUFG
      • clk1_clr_n is available as clk_out1 is the input to MBUFGCE1 and clk3_clr_n also available as clk_out3 is the input to MBUFGCE2
Sample test case with clock grouping is selected
When all the frequencies are integer divides of clk_out1
Table 6. Frequencies of Integer Divides of clk_out1 and with Multiple Clock Grouping
Clk_out DIV CLK GROUP
Clk_out1 1 CLOCK A
Clk_out2 2 CLOCK B
Clk_out3 3 Auto
Clk_out4 4 CLOCK A
Clk_out5 5 Auto
Clk_out6 6 Auto
Clk_out7 8 CLOCK B
  • Three MBUFGCE (MBUFGCE1: clkout1, 4: MBUFGCE2: clkout2, 7 and MBUFGCE3: clkout3, 6) and remaining clock (clkout5) is inferred through BUFG.
  • clk1_clr_n is available as clk_out1 is the input to MBUFGCE1, clk2_clr_n is available as clk_out2 is the input to MBUFGCE2 and clk3_clr_n is available as clk_out3 is the input to MBUFGCE3.

Following are the example combinations with Auto Buffer (Drives selected as “Buffer with CE”) and Auto Clock Grouping

  1. When all the frequencies are independent of each other (no integer division between any of them), all clock outs are inferred with separate BUFGCE
  2. When all the frequencies of integer divides of clk_out1 as in below table
    Table 7. Frequencies of integer divides of clk_out1
    Clk_out DIV
    Clk_out1 1
    Clk_out2 2
    Clk_out3 3
    Clk_out4 4
    Clk_out5 5
    Clk_out6 6
    Clk_out7 8
    • Two MBUFGCEs (MBUFGCE1: clkout1,2,4,7 and MBUFGCE2: clkout3,6) and the remaining clock (clkout6) with separate BUFGCE
    • clk1_clr_n will be available as clk_out1 is the input to MBUFGCE1, and clk3_clr_n also available as clk_out3 is the input to MBUFGCE2
    • clk1_ce will be available as clk_out1 is the input to MBUFGCE1, clk3_ce also available as clk_out3 is the input to MBUFGCE2, and clk_out5_ce is also available as BUFGCE for clk_out5
  3. When some of the frequencies are same as clk_out1, and some are integer divides of clk_out1
    Table 8. Frequencies are same as clk_out1, and some of integer divides of clk_out1
    Clk_out DIV
    Clk_out1 1
    Clk_out2 1
    Clk_out3 1
    Clk_out4 1
    Clk_out5 2
    Clk_out6 3
    Clk_out7 4
    • Three clocks (clkout1,5,7) can be derived from one MBUFGCE, and the remaining clocks (clkout2,3,4,6) will be derived from separate BUFGCE.
    • clk1_clr_n and clk1_ce will be available as clk_out1 is the input to MBUFGCE
    • clk_out2_ce, clk_out3_ce, clk_out4_ce, and clk_out6_ce are also available as 4 separate BUFGCE inferred.
  4. When only four clock outs are used and all are integer divides of clk_out1
    Table 9. Four clock out are used and all are integer divides of clk_out1
    Clk_out DIV
    Clk_out1 1
    Clk_out2 2
    Clk_out3 4
    Clk_out4 8
    • All four clocks can get from one MBUFGCE
    • clk1_clr_n and clk1_ce will be available as clk_out1 is the input to MBUFGCE
  5. When the frequencies are divided by 1 or 2
    Table 10. Frequencies are divided by 1 or 2
    Clk_out DIV
    Clk_out1 1
    Clk_out2 2
    Clk_out3 1
    Clk_out4 2
    Clk_out5 1
    Clk_out6 2
    Clk_out7 1
    • Three MBUFGCEs (MBUFGCE1: clkout1,2; MBUFGCE2: clkout3,4 and MBUFGCE3: clkout5,6) and the remaining clock (clkout7) is inferred through BUFGCE
    • clk1_clr_n, clk1_ce will be available as clk_out1 is the input to MBUFGCE1, clk3_clr_n, clk3_ce will be available as clk_out3 is the input to MBUFGCE2 and clk5_clr_n, clk5_ce will be available as clk_out5 is the input to MBUFGCE3
    • clk_out7_ce is available as BUFGCE inferred for clk_out7
  6. When all the frequencies are even integer divides of clk_out1
    Table 11. Frequencies are even integer divides of clk_out1
    Clk_out DIV
    Clk_out1 1
    Clk_out2 2
    Clk_out3 2
    Clk_out4 4
    Clk_out5 4
    Clk_out6 6
    Clk_out7 8
    • Two MBUFGCE (MBUFGCE1: clkout1,2,4,7 and MBUFGCE2: clkout3,5) should be used to infer 6 clock outs and the remaining clock (clkout6) should be inferred from BUFGCE
    • clk1_clr_n, clk1_ce will be available as clk_out1 is the input to MBUFGCE1 and clk3_clr_n, clk3_ce also available as clk_out3 is the input to MBUFGCE2
    • clk_out6_ce is available as BUFGCE will be inferred for clk_out6

Sample test case with clock grouping is selected:

When all the frequencies are integer divides of clk_out1

Table 12. Frequencies of integer divides of clk_out1
Clk_out DIV CLK GROUP
Clk_out1 1 CLOCK A
Clk_out2 2 CLOCK B
Clk_out3 3 Auto
Clk_out4 4 CLOCK A
Clk_out5 5 Auto
Clk_out6 6 Auto
Clk_out7 8 CLOCK B

Three MBUFGCEs (MBUFGCE1: clkout1,4; MBUFGCE2: clkout2,7 and MBUFGCE3: clkout3,6) and the remaining clock (clkout5) is inferred through BUFGCE

  • Three MBUFGCE (MBUFGCE1: clkout1, 4; MBUFGCE2: clkout2, 7 and MBUFGCE3: clkout3, 6) and the remaining clock (clkout5) is inferred through BUFGCE.
  • clk1_clr_n, clk1_ce will be available as clk_out1 is the input to MBUFGCE1, clk2_clr_n, clk2_ce will be available as clk_out2 is the input to MBUFGCE2 and clk3_clr_n, clk3_ce will be available as clk_out3 is the input to MBUFGCE3.
  • clk_out5_ce is available as BUFGCE inferred for clk_out5
Note: In all the above cases, the *_clr_n pin connected to MBUFGCE is active-Low signal and you should tie to 1 for MBUFGCE to be active.