Auto Primitive - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

This feature helps instantiating the clocking primitive that best fits your requirements with minimum usage of clocking resources, high performance, and better clock routing. All clocking features and optional ports would be in unselected state when you select primitive as Auto. You need to exclusively enable the options that are required. The following table explains the selection criteria depending on the clocking features that you select.

Table 1. Auto Primitives
Feature Auto Primitive Selection Selection Criteria
Phase Alignment MMCM This feature is only supported in MMCM
Dynamic Phase Shift MMCM or DPLL or MBUFGCE The selection criteria is:
  • If number of output clocks are > 4, MMCM is Auto Primitive
  • If the number of output clocks ≤ 4 and the Selected Output Clocks ≤ 500 MHz and 50% Duty Cycle, DPLL is Auto Primitive or else it is MMCM
  • If number of output clocks are <=4 and any of the clocks PI Control is selected as DESKEW_PD2, then MMCM is the Auto Primitive.
  • If number of output clocks are <=4 and none of the clocks PI Control selected as DESKEW_PD1 or DESKEW_PD2 and drives is selected as buffer and phase is 0.00 for all the clocks and duty cycle is 50 and clock grouping is auto for all the clocks. And all the used output clocks are integer divides (/1, /2, /4 or /8) to each other then MBUFGCE is Auto Primitive.
Secondary Input Clock MMCM This feature is only supported in MMCM
Number Output Clocks selected > 4 MMCM or DPLL or MBUFGCE The selection criteria is:
  • If the number of output clocks are > 4 then MMCM is set to Auto Primitive
  • If the number of output clocks ≤ 4 and the selected output clocks ≤ 500 MHz at 50% Duty Cycle, the DPLL is set to Auto Primitive or else it is set to MMCM
  • If number of output clocks are <=4 and any of the clocks DYN_PS is selected as DESKEW_PD2, then MMCM is the Auto Primitive
  • If number of output clocks are <=4 and none of the clocks PI Control selected as DESKEW_PD1 or DESKEW_PD2 and drives selected as buffer and phase is 0.00 for all the clocks. Duty Cycle is 50 and Clock Grouping is Auto for all the clocks.All the used output clocks are integer divides (/1, /2, /4 or /8) to each other then MBUFGCE is Auto Primitive.
Safe Clock Startup and Safe Clock Mode as Deskew Mode MMCM DESKEW Mode is not supported for DPLL, as clkin_deskew connection must not come from clk_out path
Non zero Phase MMCM or DPLL The selection criteria is:
  • If the number of output clocks are > 4 then MMCM is set to Auto Primitive
  • If the number of output clocks ≤ 4 and the selected output clocks ≤ 500 MHz at 50% Duty Cycle, the DPLL is set to Auto Primitive or else it is set to MMCM
Input Clock Stopped (port) MMCM This port is available only in MMCM
Clkfb_stopped (port) MMCM This port is available only in MMCM

Reset, Locked, Power_down Port

Input Frequency Ranges, Output Frequency ranges, and VCO Frequency Ranges
Note: The range values will vary depending on the part/board/speed grade selected. Refer to Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957) for DC and AC switching characteristics.
MMCM OR DPLL MMCM as AUTO_PRIMITIVE is chosen when:
  • If the number of output clocks are > 4 then MMCM is set to Auto. If the number of output clocks < 4 with random duty cycle and phase
  • If the number of output clocks < 4 and clocking software algorithm is not able to find the solution
  • If number of output clocks are <=4 and any of the clocks DYN_PS is selected as DESKEW_PD2, then MMCM is the Auto Primitive
  • If the number of output clocks ≤ 4 with random duty cycle and phase and the selected output clocks ≤ 500 MHz at 50% Duty Cycle
DPLL as AUTO_PRIMITIVE is chosen when:
Note: Reset and power down are mapped to the same port. For backward compatibility, reset is shown as a port.
Output Clocks <= 4 DPLL If Duty Cycle of all clocks = 50%
MMCM If any clock Duty Cycle != 50%
MBUFGCE If Duty Cycle of all clocks = 50% and phase of all clocks = 0 and clock grouping of all clocks is Auto and all the output clock frequencies are integer divides to each other (/1, /2, /4 and /8)

For example: Four clock outs are present with above criteria and having frequencies as ck_out1 = 200 MHz, clk_out2 = 100 MHz, clk_out3 = 50 MHz and ck_out4 = 25 MHz. In this case MBUFGCE is inferred as Auto Primitive as the clocks are divides to each other

ZHOLD DPLL The selection criteria is:

If the number of output clocks ≤ 4 with ZHOLD is enabled and the selected output clocks ≤ 500 MHz at 50% Duty Cycle, then the DPLL is set to Auto Primitive