Clock Monitor - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

The Clock Monitor feature allows you to monitor the clocks in a system; typically, the inputs to the MMCM/PLL/DPLL. It detects changes in the frequency of the clock, glitches in the clock, or a clock stop. It also gives you the option to specify the tolerance required. For example, if you want to see an error only if the frequency is 1 MHz higher than requested, a tolerance of 1 MHz must be specified as shown in the following figure.

Figure 1. Clock Monitor
Clock Stop
The Clock Stop goes High when the clock is flat-lined.
Clock Glitch
The Clock Monitor can detect a glitch in the user clock. The minimum glitch it can detect in the user clock is one clock period of the reference clock.
Note: The Clock Glitch condition might overlap with the Clock Overrun.
Clock Out of Range
The Clock Monitor detects if the user clock frequency exceeds or goes below the required frequency.
Reference Clock Frequency
The reference clock frequency determines the frequency of the clock to be monitored.
Channel Clock Frequency
You can choose the frequency of the clock to be monitored based on the value of reference clock.
Tolerance
You can program the precision required to monitor the clock.
Enable_PLL/MMCM (0-1)
Enabling this option monitors the input clock to the MMCM/PLL/DPLL.
Note:
  • If the Enable_PLL/MMCM options are enabled in the IDE, ensure that the primary/secondary clock frequency does not exceed 300 MHz.
  • s_axi* ports will be available when clock monitor is selected, and interrupt status can be read through axi registers.
  • Overrun and Underrun are termed as out-of-range errors.
  • Only integer values of tolerance are accepted.
  • Only clock frequencies (USER_CLK_FREQ_0/1/2/3) less than or equal to 300 MHz is accepted.
Clock Monitor Registers
The Clock Monitor error status register, the Interrupt status register, and the Interrupt enable register have the following bit map:
Table 1. Clock Monitor Register Bit Map
Bit Number Description
0 User clock 0 frequency is greater than the specifications.
1 User clock 1 frequency is greater than the specifications.
2 User clock 2 frequency is greater than the specifications.
3 User clock 3 frequency is greater than the specifications.
4 User clock 0 frequency is lesser than the specifications.
5 User clock 1 frequency is lesser than the specifications.
6 User clock 2 frequency is lesser than the specifications.
7 User clock 3 frequency is lesser than the specifications.
8 Glitch occurred in user clock 0.
9 Glitch occurred in user clock 1.
10 Glitch occurred in user clock 2.
11 Glitch occurred in user clock 3.
12 Clock stop on user clock 0.
13 Clock stop on user clock 1.
14 Clock stop on user clock 2.
15 Clock stop on user clock 3.
16-31 Undefined