Constraining the Core - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

Required Constraints

At least one clock constraint is required for period and jitter. The following command signifies the setting of +/- 100 ps (= 0.1 ns) peak to peak jitter on the primary clock port propagating through input port clk_in1:

create_clock -period 10.0 [get_ports clk_in1]
set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1

The core level XDC has early processing order so core level XDC constraints are applied first and then are overridden by the user-provided constraints.

Device, Package, and Speed Grade Selections

Supports all packages, speed grades and devices.

Clock Frequencies

Clock Management

The core can generate a maximum of seven output clocks with different frequencies.

Clock Placement

No clock placement constraint is provided.

Banking

Bank selection is not provided in xdc file.

I/O Standard and Placement

No I/O or placement constraints are provided.