Up to two input clocks are available for the clocking network. Buffers are optionally inserted on the input clock paths based on the buffer type that is selected.
The primitive, either user or wizard selected, is instantiated into the network. Parameters on primitives are set by the wizard, and can be overridden by the users. Unused input ports are tied to the appropriate values. Unused output ports are labeled as such.
If phase alignment is not selected, the feedback output port on the primitive
is automatically tied to the feedback input port. If phase alignment with automatic
feedback is selected, the connection is made, but the path delay is matched to that
clk_out1. If user-controlled feedback is selected, the feedback
ports are exposed.
Buffers that are user-selected are added to the output clock path, and these clocks are provided.
All ports are optional, with the exception that at least one input and one output clock are required. Availability of ports is controlled by user-selected parameters. Any port that is not exposed is either tied off or connected to a signal labeled unused in the delivered source code.