Design Environment - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English
The following figure shows the design environment provided by the wizard to assist in integrating the generated clocking network into a design. The wizard provides a synthesizable and downloadable example design to demonstrate how to use the network and allows you to place a very simple clocking network in the device. A sample simulation test bench, which simulates the example design and illustrates output clock waveforms with respect to input clock waveforms, is also provided.
Figure 1. Clocking Network and Support Modules