Deskew Feature Support for Versal - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

The Clocking Wizard provides a drop-down menu for each clock-out for you to select DESKEW_PD1 or DESKEW_PD2 in PI Control column. Based on your choice, the CLKOUTx_PHASE_CTRL is set accordingly to 2’b01 (for network 1/PD1) or 2’b11 (for network 2/PD2) or 2'b10 for Fine_PS or 2'b00 for None. The following table describes primitive and number of deskew network details:

Table 1. Primitive Vs. Deskew Network
Primitive Number of DESKEW Networks Dyn_PS Option
MMCM 2 DESKEW_PD1 and DESKEW_PD2
XPLL (PLL) 2 DESKEW_PD1 and DESKEW_PD2
DPLL 1 DESKEW_PD1
AUTO** 2 DESKEW_PD1 and DESKEW_PD2
  1. AUTO primitive can be MMCM/DPLL/MBUFGCE depending on the selected PI Control option.
Deskew Connection implementations and Prerequisites
  • In any primitive, clkin_deskew and clkfb_deskew must have the same frequency
  • clkfb_deskew connection is in the feedback path from one of the clock out (which is selected as deskew)
  • The buffer in the feedback path can be either BUFG, BUFGCE, BUFGCE_DIV or MBUFGCE buffer
  • In the case of No_Buffer selected for the clock out that wants to be connected to clkfb_deskew, then the clkfb_deskew port gets exposed and the connection to clkfb_deskew must be provided by you with any buffer based on the requirement
  • In DPLL, clkin and clkin_deskew should always be tied
  • In MMCM or XPLL, clkin_deskew connection must be made as MUX between clkin signal [It can be clk_in1 (which means 0 to be chosen as DESKEWx_IN) or clk_in2 (which means 9 to be chosen as DESKEWx_IN)] and any of the clock output (in which case any value from 1 to 7 can be chosen for DESKEWx_IN) and external clock (8 to be chosen as DESKEWx_IN).
  • Whenever DESKEWx_IN is chosen as "8" or clk_ext which means clkin1_deskew/clkin2_deskew will be exposed as port and the connection will be made to clkin_deskew port of primitive. User must ensure the frequency of the clkin_deskew to be same as clkfb_deskew even in the case of external clock selection.

The Clocking Wizard core provides an interface to select programmable delay for deskew network 1 or 2. Based on your choice, DESKEW_DLY_ENx/DESKEW_DLY_PATHx, DESKEW_DELAYx and DESKEWx_IN/DESKEWx_FB attributes are set accordingly. You can program the delay in number of taps in the range provided by the wizard. DESKEW1_IN, DESKEW1_FB, DESKEW2_IN and DESKEW2_FB values are used to connect clkin1_deskew, clkfb1_deskew, clkin2_deskew and clkfb2_deskew respectively. The range of DESKEWx_IN is from 0 to 9 which means, if you want to connect clkinx_deskew to primary input clock, you need to select it as 0 and if it is secondary input clock, you need to select it as 9, and you need to select as 8 if you want to connect clkinx_deskew with external/outside clkin_deskew and if it is clk_out <1-7> then values <1-7> can be selected. The range of DESKEWx_FB is from 1 to 7 which means, if clkfbx_deskew needs to be connected from any of the clock out you need to provide respective value. If it is clk_out <1-7> then values <1-7> has to be provided. There are few limitations set by the wizard to configure deskew networks on different clock outputs. The following are some examples:

  • Consider selecting three clock outputs such as clk_out1 = 100 MHz, clk_out2 = 200 MHz, and clk_out3 = 250 MHz. If you select PI Control for clk_out1 to be DESKEW_PD1, then there is no option of DESKEW_PD1 for clk_out3 as the frequency of clk_out3 is not integer multiple/divider of clk_out1. Whereas both the options of DESKEW_PD1 and DESKEW_PD2 can be chosen for clk_out2 as the frequency of clk_out2 is integer multiple/divider of clk_out1.
  • Similarly, if you select PI Control for clk_out2 to be DESKEW_PD2, then neither DESKEW_PD1 nor DESKEW_PD2 option is provided for clk_out3 as the frequency of clk_out3 is different from clk_out2 and clk_out1 and also the frequency is neither integer multiple/divider of clk_out1 nor that if clk_out2.
  • DESKEW_PD2 is provided as an option for clk_out3 if DESKEW_PD2 is not selected for clk_out2.
Note: For more information on Deskew, see Chapter-4 in Versal ACAP Clocking Resources Architecture Manual (AM003).