Detailed Example Design - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

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1.0 English

In Vivado® design tools, the open_example_project [get_ips <component_name>] parameter in tcl console invokes a separate example design project where it creates <component_name>_exdes as top module for synthesis and <component_name>_tb as top module for simulation. You can run implementation or simulation of the example design from example project.