Digital Deskew for DPLL - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

The clocking wizard provides a drop-down menu for each clk_out starting from clk_out 1 to 3 for you to select DESKEW_PD1 from the PI control column. When you select this option, 2’b01 is set to CLKOUTx_PHASE_CTRL parameter.

When you select DPLL deskew feature, reset and power_down ports are exposed automatically and these signals must pass through a calibrated soft logic present inside the IP. Whenever the soft logic is enabled, PERF_MODE of the primitive is set to FULL by the IP. Then the outputs of the calibrated logic are connected to the DPLL primitive. Clock input connection to the DPLL must be a ref_clk connection on the calibrated soft logic. This feature/calibration logic implementation helps you to get the proper clock output without any glitches. Following is the schematic with digital deskew in DPLL enabled:

Figure 1. Digital Deskew Enabled Schematic