Directory and File Contents - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

The open_example_project [get_ips <component_name>] parameter creates the example_project directory in the working area.

Example design contains the counters on all the output clocks and MSBs of these counters are used as output to observe on LEDs on board.

The following file describes the example design for the Clocking Wizard core.

Verilog

<project_name>/<project_name>.srcs/sources_1/ip/<component_name>/example_design/<component_name>_exdes.v
The top-level example designs adds clock buffers where appropriate to all of the input and output clocks. All generated clocks drive counters, and the high bits of each of the counters are routed to a pin. This allows the entire design to be synthesized and implemented in a target device to provide post place-and-route gate-level simulation.
Note: Example design files are delivered only in Verilog.