The Clocking Wizard core provides an AXI4-Lite interface for the dynamic reconfiguration of the clocking primitive MMCM/XPLL/DPLL. This interface is enabled when Dynamic Reconfiguration is enabled. Mixed language RTL is delivered by the core when AXI4-Lite interface is used.
Register Space provides details of the signals of AXI4-Lite and the tables in the Register Space section provide details of the clock configuration registers.
The Clocking Wizard core uses a configuration state machine listed in and extends from two fixed state configuration to program any valid range of multiply, divide, phase, and duty cycle. In this state machine, State 1 corresponds to default state configured through Clocking Wizard interface. State 2 corresponds to user-configuration loaded into the clock configuration register detailed in the tables in Register Space. State 2 values are also initialized with the State 1 values so that a valid configuration is stored by default. All the dynamic reconfiguration registers are to be updated whenever you want to reprogram the clock.
Perform the following steps for dynamic reconfiguration:
- Generate the Clocking Wizard IP enabling dynamic reconfiguration.
- Open another Clocking Wizard with the same input clock and the features as intended.
- Now, change the output clock features in the output clock tab of the Vivado® IDE as required for dynamic reconfiguration.
- Generate the IP.
- A file with name <component_name>_drp_address_map gets generated in the IP sources area. This file has the address and the data which needs to be written into AXI interface for reconfiguring.
- After writing all the registers in the file, now write address
0x03as mentioned in the register map to initiate the reconfiguration.
An example of this feature has been described in the following section.
Example for Dynamic Reconfiguration through AXI4-Lite
The input and output clock frequencies are 100 MHz in the Clocking Wizard by default.
- The output clock frequency needs to be reconfigured to 50 MHz with a phase shift of 90 degrees.
- The file gets generated in the sources area as shown below.
- The file specifies all the AXI Registers with the address and the data which needs to be written into it. Configure all the AXI Registers with respect to the table.
- Configure the address: C_BASEADDR + 0x014 with
0x00000003to set the LOAD and SEN bits.
- Wait for the locked signal. The new frequency can be checked at
- DRP interface is not supported for Versal® devices, APB3 interface is used internally. For details on DRP/APB3 ports, see Versal ACAP Clocking Resources Architecture Manual (AM003).
- While reconfiguring, even reconfiguring for one clock output, all other active clock outputs will be reset.