Features - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

The Clocking Wizard for VersalĀ® adaptive compute acceleration platforms (ACAPs):

  • Offers a mixed-mode clock manager (MMCM) and different phase-locked loop (XPLL/DPLL) primitives. GUI options must be enabled for using supported primitive features.
  • Provides guidance for selecting the appropriate clocking primitive based on your requirements.
  • Accepts up to two input clocks and up to seven output clocks per clock network.
  • Provides AXI4-Lite interface for dynamically reconfiguring the clocking primitives for multiply, divide, phase shift/offset, or duty cycle programmability.
  • Automatically calculates voltage-controlled oscillator (VCO) frequency for primitives with an oscillator, and provides multiply and divide values based on input and output frequency requirements.
  • Automatically implements overall configuration that supports phase shift and duty cycle requirements.
  • Inserts the buffer needed for input and output clocks.
  • Provides the ability to override the selected clock primitive attributes.
    Note: The user should be cautious when override mode is selected, and ensure all the overwritten values will fall into valid values and a valid VCO/PFD frequencies range.
  • Provides a synthesizable example design including the clocking network and a simulation test bench.
  • Provides optional ports for the selected primitive.
  • Input and output ports can be renamed as per the user's requirements.