General Checks - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

Ensure that all the timing constraints for the core were properly incorporated from the example design and that all constraints were met during implementation.

  • Does it work in post-place and route timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue. Ensure that all clock sources are active and clean.
  • If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the locked port.
  • If your outputs go to 0, check your licensing.

Known Issues

  • Run connection automation in IPI is still under development.
  • Phase parameter does not propagate to the Port when OVERRIDE mode is set in IPI.
  • When jitter value is switched between PS and UI, the resulted values are sometimes incorrect.