General Design Guidelines - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English
  • Provide the available input clock information for frequency and jitter.
  • If the same input clock is used by another logic, and is also the output of the global buffer, then provide the no buffer or global buffer option for the source type. If the input clock is used only by the core, then provide a clock-capable pin as the source type.