MBUFGCE Enhancements - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

When MBUFGCE is selected explicitly, or IP Inferred MBUFGCE, a new Parameter CE_SYNC_EXT will be available to the user. MBUFGCE Inference by IP happens on selecting either "Buffer" or "Buffer with CE." There are MODEL PARAMETERS for getting information on how many MBUFGCE are inferred (C_AUTO_NUMMBUFGCE) and which clocks are connected through MBUFGCE (C_CLK_TREE<1-7>). The user will get all this information from the summary table of GUI.

CLRB_LEAF pin on MBUFGCE is active low asynchronous clear, used to reset BUFDIV_LEAF clock dividers of MBUFGCE.

The optimal circuit will help synchronize CE and CLRB_LEAF pins of MBUFGCE to LOCKED and Reset signals, guaranteeing the correct startup behavior of the MBUFGCE Clock outputs.

You can select "CE and CLR SYNC EXTERNAL TO CORE" from Output Clocks Tab to have the circuitry outside the IP. The default value of CE_SYNC_EXT is false. This means an optimal circuit needs to be implemented by IP Core inside the wizard.

The user needs to set the parameter to true if the user wants to implement a synchronized structure outside IP. In that case, IP will directly get those signals from outside and will feed to respective signals of CE and CLRB_LEAF signals of MBUFGCE.

Note: For more details please refer:
  • Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)
  • Versal ACAP Clocking Resources Architecture Manual (AM003)