Migrating - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

This information is provided to assist those designers who are experienced with the DCM and PLL Architecture Wizards. It highlights the differences between the old and new cores.

Migrating to the Vivado Design Suite

For information about migrating to the Vivado® Design Suite, see ISE to Vivado Design Suite Migration Guide (UG911).

Note: You cannot migrate to a Versal® Clocking Wizard from a Non- Versal® Clocking Wizard as they both are two separate IPs. A new IP must be built from scratch with similar properties. .

For example, a user has a requirement of two output clocks with clk_out1 as 120 MHz and clk_out2 as 150MHz and a separate phase/duty cycle requirement for two clocks. In Non-Versal, the user will pass a value for each clock attribute, whereas, in Versal, the parameters must be provided as a string for all the output clocks when using batch mode. For example, if you want to feed the requested clock frequencies for the clocks, the parameter CLKOUT_REQUESTED_OUT_FREQ must be assigned a value of 120, 150, 100, 100, 100, 100, and 100. (100 is the default value) It is the combination of all output frequencies from 1 to 7. If the string does not contain 7 values, it fills the initial frequencies, and for the rest, it takes the default value. Similarly, for all other parameters of CLKOUT_DRIVES, CLKOUT_DYN_PS, CLKOUT_MATCHED_ROUTING, CLKOUT_REQUESTED_DUTY_CYCLE, CLKOUT_REQUESTED_PHASE, CLKOUT_USED, and CLKOUT_PORT, you must pass the respective values as a list of values in batch mode instead of a single value for each clock.

PRIMITIVE, which can be “MMCM, PLL, Auto” in Non-Versal, can be mapped to the PRIMITIVE_TYPE parameter.

OVERRIDE_MMCM, which can set to “True/False” should map to the OVERRIDE_PRIMITIVE parameter.