Output Clock Ports - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English
Table 1. Clocking Wizard Output Clock Ports
Port Name I/O Description
clk_out1 Output Clock Out 1: Output clock of the clocking network. clk_out1 is not optional.
clk_out1_ce Input Clock Enable: Clock enable pin of the output buffer. Available when the BUFGCE or BUFGCE_DIV or MBUFGCE buffers are used as output clock drivers.
clk_out1_clr Input Counter reset for divided clock output: Available when the BUFGCE_DIV buffer is used as output clock driver.

clk_out1_clr is active-High signal.

clk_out1_clr_n Input Counter reset for divided clock output: Available when the MBUFGCE buffer is used as output clock driver. It is an active-Low signal.
clk_out[2-n]_ce Input Clock Enable: Clock enable pin of the output buffer. Available when the BUFGCE or BUFGCE_DIV or MBUFGCE buffers are used as output clock drivers.
clk_out[2-n]_clr_n Input Counter reset for divided clock output: Available when the MBUFGCE buffer is used as output clock driver. It is an active-Low signal.
clk_out[2-n]_clr Input Counter reset for divided clock output: Available when BUFGCE_DIV buffer is used as output clock driver.

clk_out [2-n]_clr is active-High signal.

clkfb_out Output Clock Feedback Out: Single ended feedback port of the clocking primitive. Available when the user-controlled feedback or automatic control off chip with single ended feedback option is selected.
clkfb_out_p Output Clock Feedback Out: Positive and Negative: Differential feedback output port of the clocking primitive. Available when the user-controlled off-chip feedback and differential feedback option is selected.
clkfb_out_n
clk[1-7]_clr_n Input

Clock CLR: Clock clear pin. Available when the buffer (auto buffer, either "Buffer" or "Buffer with CE" ) is used as output clock drive and one clr_n pin is available for one MBUFGCE. Which clr_n pin is available depends on the tree clock and leaf clocks of that MBUFGCE.

For example: Two clock outs are present and clk_out1 = 200 MHz and clk_out2 = 100 MHz and drives selected as buffer for both the clocks. And clock grouping is same for both the clocks as both the output frequencies are integer dividers to each other which can be inferred from MBUFGCE and here, clk_out1 is tree and clk_out2 is leaf clock derived from it. So, clk1_clr_n will be available in this case.

This is active-Low signal, and you should tie to 1 for MBUFGCE to be active.

clk[1-7]_ce Input

Clock CE: Clock CE pin. Available when the buffer (auto buffer, which means "Buffer with CE") is used as output clock drive, and one CE pin is available for one MBUFGCE. Which CE pin is available depends on the tree clock and leaf clocks of that MBUFGCE.

For example, two clock outs are present and clk_out1 = 200 MHz and clk_out2 = 100 MHz and drives selected as "Buffer with CE" for both the clocks.

And clock grouping is the same for both the clocks as both the output frequencies are integer dividers, which can be inferred from MBUFGCE, and here, clk_out1 is a tree, and clk_out2 is leaf clock derived from it. So, clk1_ce will be available in this case.

This is an active-High signal, and you should tie to 1 for MBUFGCE to be active.