Output Clock Settings - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

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1.0 English

The second page of the GUI (the following figure) configures requirements for the output clocks. Each selected output clock can be configured on this screen.

Figure 1. Output Clocks

Configuring Output Clocks

To enable an output clock, click on the box located next to it. Output clocks must be enabled sequentially. You can now rename the output clocks in the output clock table itself.

You can specify values for the output clock frequency, phase shift, and duty cycle assuming that the primary input clock is the active input clock. You can select drives, clock grouping and PI control for each output clock. The Clocking Wizard attempts to derive a clocking network that meets your criterion exactly. In the event that a solution cannot be found, best attempt values are provided and are shown in the actual value column. Actual frequencies are calculated to limit the values to five decimal places. Achieving the specified output frequency takes precedence over implementing the specified phase, and phase takes higher precedence over duty cycle in the clock network derivation process. The precedence of deriving the circuits for the clk_out signals is clk_out1 > clk_out2 > clk_out3 and so on. Therefore, finding a solution for clk_out1 frequency has a higher priority. Values are recalculated every time an input changes. Because of this, it is best to enter the requirements from top to bottom and left to right. This helps to pinpoint requested values that cannot be supported exactly. If phase alignment is selected, the phase shift is with respect to the active input clock.

Note: In the Versal ACAP Clocking Wizard, there are no individual parameters for each clock. The parameters must be provided as a string for all the output clocks when using batch mode. For example, if you want to feed the requested clock frequencies for the clocks, the parameter CLKOUT_REQUESTED_OUT_FREQ must be assigned a value of 120, 100, 300, 450, 200, 100, and 380. It is the combination of all output frequencies from 1 to 7. If the string does not contain 7 values, it fills the initial frequencies and takes the default values for the rest. The entire table in "Output Clocks" Tab is a single widget, and the SW takes the information. The user must either click "Calculate Actual Values" button below the table or move the cursor outside the widget. This is a JAVA Widget restriction, which intern helps the processing to be fast.
Note: For BUFGCE_DIV, DIVIDER value is set to 1. To use other values, select "No_buffer" and generate IP. Use Utility_buffer to select BUFGCE_DIV and pass the needed DIV value.

Reset Type

You can select Reset Type as active-High or active-Low when RESET is enabled. Default value is active-High.

Choosing Feedback

Feedback selection is only available when phase alignment is selected. When phase alignment is not selected, the output feedback is directly connected to the input feedback. For designs with phase alignment, choose automatic control on-chip if you want the feedback path to match the insertion delay for CLK_OUT1. You can also select user-controlled feedback if the feedback is in external code. If the path is completely on the FPGA, select on-chip; otherwise, select off-chip. For designs that require external feedback and related I/O logic, choose automatic control off-chip feedback. You can choose either single-ended or differential feedback in this mode. The wizard generates the core logic and logic required to route the feedback signals to the I/O.

Feedback Signaling

When the Phase Alignment feature is enabled, the automatic control on-chip Clkfb_in and Clkfb_out ports are not exposed in the IP.
Figure 2. Automatic Control on-Chip
Figure 3. Automatic Control off-Chip
Figure 4. User Controlled ON or OFF Chip
When the Phase Alignment feature is disabled, the Clkfb_in and Clkfb_out ports are not exposed to the IP. CLKFBIN is directly connected to CLKFBOUT.

Phase Shift Mode

Select whether the phase-shifted clock should be modeled into the clock waveform or latency. No multicycle constraint is needed when modeled through latency. The PHASE_SHIFT_MODE property is set in the generated XDC. For more information, see Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

For more information on Phase Shift Mode, see Versal ACAP Clocking Resources Architecture Manual (AM003).