Output Clocks - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English
The number of output clocks is user-configurable. The maximum number allowed depends upon the selected device or primitive and the interaction of the major clocking features you specify. For MMCM, a maximum of seven, and for XPLL and DPLL, a maximum of four output clocks can be configured. If the primitive selected is Auto, all the seven output clocks can be configured. Input the desired timing parameters (frequency, phase, and duty cycle) and let the Clocking Wizard select and configure the clocking primitive and network automatically to comply with the requested characteristics. If it is not possible to comply exactly with the requested parameter settings due to the number of available input clocks, best-attempt settings are provided. When this is the case, the clocks are ordered so that clk_out1 is the highest-priority clock and is most likely to comply with the requested timing parameters. The wizard prompts you to set the frequency parameter settings before setting the phase and duty cycle settings.
Tip: The port names in the generated circuit can differ from the port names used on the original primitive.