Port Descriptions - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

The following table describes the input and output ports provided from the clocking network. All ports are optional, with the exception being that at least one input and one output clock are required. The options selected determine which ports are actually available to be configured. For example, when PI Control is selected as Fine_PS, the psclk, psen, psincdec, and psdone ports are exposed. Any port that is not exposed is appropriately tied off or connected to a signal labeled unused in the delivered source code.