Resets - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English
  • The Clocking Wizard has an active-High asynchronous reset signal for the clocking primitive.
  • The core must be held in reset during clock switch over.
  • When the input clock or the feedback clock is lost, the input_clk_stopped or clkfb_stopped status signal is asserted. After the clock returns, the input_clk_stopped signal is de-asserted and a reset must be applied.