- The Clocking Wizard has an active-High asynchronous reset signal for the clocking primitive.
- The core must be held in
resetduring clock switch over.
- When the input clock or the feedback clock is lost, the
clkfb_stoppedstatus signal is asserted. After the clock returns, the
input_clk_stoppedsignal is de-asserted and a
resetmust be applied.