Safe Clock Startup - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

This feature enables a stable and valid clock at the output using BUFGCE after Locked is sampled High for eight input clocks.

Following are the options that will be enabled when this option is selected.

Figure 1. Output Clocks with Safe Clock Startup and Clock Sequencing for MMCM

You can configure the sequence number from 1 to the maximum number of clocks selected. The Clocking Wizard does not allow any break in the sequence from one to the maximum in the table. The frequency of the output clock in the sequence must not be more than eight times that of the output clock next in sequence.

Reset and Locked Ports are available as soon as this option is selected as the mentioned signals will be used to implement safe clock circuitry.

The safe clock startup circuit will vary depending on the safe clock startup mode you choose.

Safe Clock Startup Mode

This mode selection will determine how the hardware structure should be for selected outputs.

The options for this mode are:

  1. DESKEW_MODE
  2. BUFGCE_MODE

DESKEW_MODE will help operate the clocking circuit for high frequencies compared to BUFGCE_MODE selection. Hence, DESKEW_MODE is the default value for this parameter.

But, DESKEW_MODE cannot be selected if the user has more than 2 output clocks in MMCM/XPLL (As there are a maximum of two deskew networks present for MMCM/PLL), and this mode is not supported for DPLL because of Deskew connection rules restriction.

Versal offers a new CE_TYPE property, which lets you specify if the CE input to the BUFGCE is timed (CE_TYPE=SYNC) or uses an internal 3-stage synchronizer (CE_TYPE=HARDSYNC). In the case of HARDSYNC, the CE path is not timed (CE timing arc disabled), and the BUFGCE is enabled within 3 or 4 clock cycles. However, there is no guarantee that all the BUFGCE in a clock region that employ the CE_TYPE=HARDSYNC 3-stage synchronizer are enabled within the same number of clock cycles.

Figure 2. Schematic for safe clock startup in Deskew Mode for MMCM
Figure 3. Schematic for safe clock startup in BUFGCE mode
Figure 4. Schematic with the sequencing of four clocks
Note:
  • DESKEW_MODE will not be possible in DPLL, as clkin_deskew connection in DPLL must be from clock input. So, In DPLL, Only BUFGCE Mode will be allowed
  • When the user selects DESKEW_MODE, set CE_TYPE to SYNC
  • When the user selects BUFGCE_MODE, by default, CE_TYPE is set to HARDSYNC, but the user can change the value to other CE Type.
  • In any Mode, Timing is not guaranteed beyond a certain frequency (Frequency will vary for each speed grade)
  • In DESKEW_MODE, the user needs to manually modify or adjust the deskew delay to improve the timing to resolve the timing issue.
  • For more details, refer Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)