Summary - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

The summary page, shown in the following figure, contains general summary information. The Summary page gives you the information about the connections between the wizard output clocks and the primitive output clocks. The source column in the last table specifies the primitive output pin. It states whether the clock is generated directly from the primitive or derived using MBUFGCE. The Buffer column in the last table specifies the buffer that drives the output clock. IP will infer the buffer optimally in case of Auto buffer selected by user. The Clock Group in the last table specifies the clock group selected for that output clock. The CLR Pin connection in the last table will give CLR Pin information for each clock. This information is significant when BUFGCE_DIV or MBUFGCE are selected explicitly and also when Auto Buffer ("Buffer" or "Buffer with CE") is inferred from MBUFGCE. The CE pin connection in the table will give the information of CE pin for each clock. This information is significant when BUFGCE or BUFGCE_DIV or MBUFGCE or "Buffer with CE" is selected. Divider value, TSpread, Phase Error and Pk-to-Pk Jitter columns in the table will give the information on the divider value, TSpread, Phase Error and Pk-to-Pk Jitter for each clock out respectively. Tspread is the actual spread, as calculated in Spread Spectrum.

Figure 1. Summary Screen

Resource Estimate Summary

A resource estimate is provided based on the chosen clocking features.

Input Clocking Summary

Information entered on the first page of the GUI is shown for the input clocks.

Output Clocking Summary

Derived timing information for the output clocks is shown. If the chosen primitive has an oscillator, the VCO frequency is provided as reference. If you have a secondary input clock enabled, you can choose which clock is used to calculate the derived values.

Port Names

The Clocking Wizard allows you to name the ports according to their use. If you want to name the HDL port for primary clock input, simply type in the port name in the adjacent text box. The text boxes contain the default names. In the case of primary clock input, the default name is CLK_IN1.
Important: Be careful when changing the port names as it could result in syntax errors if the port name entered is any reserved word of VHDL or Verilog or if that signal is already declared in the module.