This chapter contains information about the provided test bench in the Vivado® Design Suite environment.
The following file describes the demonstration test bench.
demonstration test bench is a simple Verilog program to exercise the example design and the
core. It does frequency calculation and check of all the output clocks. It reports all the
output clock frequency and if any of the output clocks is not generating the required
frequency, it reports an error.
Note: Test bench files are delivered only in Verilog.