Unsupported Features in Example Design - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

Example design is not supported for:

    • DPLL primitive when Deskew is used, and "LOCKED_FB" is disabled. Enable "LOCKED_FB" for generating example design.
    • DPLL primitive when both Deskew and Dynamic reconfiguration is enabled. Disable either of them to generate an example design.
    • An example design is not supported when Clock Monitor is enabled and Primitive as None.