User Parameters - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

Document ID
PG321
Release Date
2022-04-20
Version
1.0 English

The following table shows the relationship between the fields in the Vivado® IDE and the user parameters (which can be viewed in the tool command language (Tcl) console).

Table 1. User Parameter Description
Vivado IDE Parameter/Value User Parameter/Value Default Value
Component Name COMPONENT_NAME Clk_wizard_0
Primitive

Range: MMCM, PLL, DPLL, Auto, and None

PRIMITIVE_TYPE MMCM
Phase Alignment

Range: TRUE, FALSE

USE_PHASE_ALIGNMENT FALSE
Minimize Power

Range: TRUE, FALSE

USE_MIN_POWER FALSE
Jitter_Optimization

Range:

JITTER_SEL Balanced
Display Name Actual Value
Balanced No_Jitter
Minimize Output Jitter Min_O_Jitter
Maximize Input Jitter filtering Max_I_Jitter
Secondary

Range: TRUE, FALSE

USE_INCLK_SWITCHOVER FALSE
Port Name

PRIMARY_PORT,

SECONDARY_PORT

PRIMARY_PORT Clk_in1

SECONDARY_PORT Clk_in2

Primary Input Clock (MHz)

Range (Default): 10-1230 (range vary depending on the part/board type selected)

PRIM_IN_FREQ 100.000
Secondary Input Clock (MHz)

Range (Default): 72-144

SECONDARY_IN_FREQ 100.000
Jitter Options

Range: UI, PS

JITTER_OPTIONS UI
Primary Input Jitter

Range:

PS:[10-999]UI :[0.001-0.10]

CLKIN1_ JITTER 0.010
Secondary Input Jitter

Range:

UI :[0.001-0.10]

PS:[10-999]

CLKIN2_ JITTER 0.010
Source

Range:

  • 1-Single ended Clock Capable pin
  • 2-Differential ended Clock capable pin
  • 3-Global Buffer
  • 4-No Buffer
PRIM_SOURCE Single-ended clock capable pin
Source

Range:

  • 1-Single ended Clock Capable pin
  • 2-Differential ended Clock capable pin
  • 3-Global Buffer
  • 4-No Buffer
SECONDARY_SOURCE Single-ended clock capable pin
Clk_out<1-7>

Range: True, False

CLKOUT_USED TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
Port Name

Range: True, False

CLKOUT_PORT clk_out1, clkout2, clk_out3, clk_out4, clk_out5, clk_out6, clk_out7
Requested Output clock frequency CLKOUT_REQUESTED_OUT_FREQ 100.000, 100.000, 100.000, 100.000, 100.000, 100.000, 100.000
Requested Phase

Range: -360:360

CLKOUT_REQUESTED_PHASE 0.000, 0.000,0.000, 0.000, 0.000, 0.000, 0.000
Requested Duty Cycle

Range: 0.001:99.99

CLKOUT_REQUESTED_DUTY_CYCLE Default Value: 50.0, 50.0, 50.0, 50.0, 50.0, 50.0, 50.0
Drives

Range: BUFG, BUFGCE, BUFGCE_DIV, MBUFGCE, Buffer, Buffer with CE, and No_buffer

CLKOUT_DRIVES BUFG, BUFG,BUFG, BUFG, BUFG, BUFG
PI Control

Range: DESKEW_PD1, DESKEW_PD2, Fine_PS, and None

CLKOUT_DYN_PS None, None, None, None, None, None, None
Clock Grouping

Range: Auto, CLOCK_A, CLOCK_B, CLOCK_C and None

CLKOUT_GROUPING Auto, Auto, Auto, Auto, Auto, Auto, Auto
Source

Range:

FEEDBACK_SOURCE Automatic Control On-Chip
Display Name Actual Parameter
Automatic Control On-Chip FDBK_AUTO
Automatic Control Off-Chip FDBK_AUTO_OFFCHIP
User-Controlled On-Chip FDBK_ONCHIP
User-Controlled Off-Chip FDBK_OFFCHIP
Signaling

Range:

- Single-ended: SINGLE

- Differential: DIFF

CLKFB_IN_SIGNALING Single-ended
Reset

Range: True, False

USE_RESET False
Powerdown

Range: True, False

USE_POWER_DOWN False
Input clk stopped

Range: True, False

USE_INCLK_STOPPED False
Locked

Range: True, False

USE_LOCKED False
Locked_FB

Range: True, False

USE_LOCKED_FB False
Locked_DESKEW1

Range: True, False

USE_LOCKED_DESKEW1 False
Locked_DESKEW2

Range: True, False

USE_LOCKED_DESKEW2 False
deskew1_delay_en

Range: True, False

DESKEW1_DELAY_EN False
deskew2_delay_en

Range: True, False

DESKEW2_DELAY_EN False
deskew1_delay_path

Range: ClkIn Path, ClkFb Path

DESKEW1_DELAY_PATH ClkFb Path
deskew1_delay

Range: 0-63

DESKEW1_DELAY 0
deskew2_delay_path

Range: ClkIn Path, ClkFb Path

DESKEW2_DELAY_PATH ClkFb Path
deskew2_delay

Range: 0-63

DESKEW2_DELAY 0
Clkfbstopped

Range: True, False

USE_CLKFB_STOPPED False
Reset Type

Range: active-High, active-Low

RESET_TYPE active-High
Phase shift Mode

Range: WAVEFORM, LATENCY

PHASESHIFT_MODE LATENCY
Allow Override Mode

Range: True, False

OVERRIDE_PRIMITIVE False
Bandwidth

Range:

MMCM: LOW, HIGH, OPTIMIZED

PLL: LOW, HIGH, OPTIMIZED

DPLL: OPTIMIZED

BANDWIDTH OPTIMIZED
CLKFBOUT_MULT

Range: Depends on the primitive selected

CLKFBOUT_MULT 30
CLKFBOUT_PHASE

Range: (-360.000:360.00)

CLKFBOUT_PHASE 0.000
COMPENSATION

Range:

DPLL: INTERNAL AUTO, BUF_IN, EXTERNAL

PLL: INTERNAL

MMCM: AUTO, INTERNAL, BUF_IN, EXTERNAL

COMPENSATION AUTO
DIVCLK_DIVIDE

Range: Depends on the primitive selected

DIVCLK_DIVIDE 1
CLKFBOUT_PHASE_CTRL

Range: None, Fine_PS, DESKEW_PD1, DESKEW_PD2

CLKOUTFB_PHASE_CTRL None
Divide CLKOUT<1-7>_DIVIDE 30
Duty Cycle

Range: 0-100

CLKOUT<1-7>_ DUTY_CYCLE 0.500
Phase

Range: -360:360

CLKOUT<1-7>_ PHASE 0.000
Locked LOCKED_PORT Locked
Clk_in_sel CLK_IN_SEL_PORT Clk_in_sel
Reset RESET_PORT reset
Input_clk_stopped INPUT_CLK_STOPPED_PORT Input_clk_stopped
Clkfb_stopped CLKFB_STOPPED_PORT Clkfb_stopped
Locked_FB LOCKED_FB_PORT locked_fb
Locked_DESKEW1 LOCKED_DESKEW1_PORT locked_deskew1
Locked_DESKEW2 LOCKED_DESKEW2_PORT locked_deskew2
Power_Down POWER_DOWN_PORT power_down
Dynamic Reconfig

Range: TRUE, FALSE

USE_DYN_RECONFIG FALSE
Spread Spectrum

Range: TRUE, FALSE

USE_SPREAD_SPECTRUM FALSE
Enable Clock Monitoring

Range: TRUE, FALSE

ENABLE_CLOCK_MONITOR FALSE
ZHOLD

Range: TRUE, FALSE

ZHOLD FALSE
Ss Mode

Range:

  • CENTER HIGH
  • CENTER LOW
  • DOWN HIGH
  • DOWN LOW
SS_MODE CENTER HIGH
Modulation Freq

Range: 25-250

SS_MOD_FREQ 250
Dynamic Reconfig Interface Options

Range: Enable_AXI, Enable_APB3

INTERFACE_SELECTION Enable_AXI
Enable User Clock0

Range: TRUE, FALSE

ENABLE_SUER_CLOCK0 FALSE
Enable User Clock1

Range: TRUE, FALSE

ENABLE_SUER_CLOCK1 FALSE
Enable User Clock2

Range: TRUE, FALSE

ENABLE_SUER_CLOCK2 FALSE
Enable User Clock3

Range: TRUE, FALSE

ENABLE_SUER_CLOCK3 FALSE
User clk0 Freq

Range: 1-300

USER_CLK_FREQ0 100
User clk1 Freq

Range: 1-300

USER_CLK_FREQ1 100
User clk2 Freq

Range: 1-300

USER_CLK_FREQ2 100
User clk3 Freq

Range: 1-300

USER_CLK_FREQ3 100
Enable PLL0

Range: TRUE, FALSE

Enable_PLL0 FALSE
Enable PLL1

Range: TRUE, FALSE

Enable_PLL1 FALSE
Ref clk Freq

Range: 1-300

REF_CLK_FREQ 100
Precision

Range: 1-100

PRECISION 1
Relative Inclk

Range: REL_PRIMARY, REL_SECONDARY

RELATIVE_INCLK REL_PRIMARY
Deskew1 IN

Range: 0-9

DESKEW1_IN 0
Deskew1 FB

Range: 1-7

DESKEW1_FB 1
Deskew2 IN

Range: 0-9

DESKEW2_IN 0
Deskew2 FB

Range: 1-7

DESKEW2_FB 1
Safe Clock Startup

Range: TRUE, FALSE

USE_SAFE_CLOCK_STARTUP FALSE
Safe Clock Startup Mode

Range: DESKEW_MODE, BUFGCE_MODE

SAFECLOCK_STARTUP_MODE DESKEW_MODE
CE TYPE

Range: SYNC, ASYNC, HARDSYNC

CE_TYPE SYNC
BUFGCE DIV CE TYPE

Range: SYNC, HARDSYNC

BUFGCE_DIV_CE_TYPE SYNC
CE and CLR SYNC Circuit External to Core

Range: FALSE, TRUE

CE_SYNC_EXT FALSE
Use Clock Sequencing

Range: FALSE, TRUE

USE_CLOCK_SEQUENCING FALSE
CLKOUT<1-7>_SEQUENCE_NUMBER

Range: 1-7

CLKOUT<1-7>_SEQUENCE_NUMBER 1
  1. Parameter values are listed in the table where the Vivado IDE parameter value differs from the user parameter value. Such values are shown in this table as indented below the associated parameter.