This register need to be programmed as per the streams executed as part of a batch for memory based mode. Bit 0 is for stream 1, bit 1 is for stream 2, likewise bit 7 is for stream 8. This register is not applicable for stream base mode operation of the IP as there is only one stream.
Important: The registers related to the first input stream are described above, the same description is applicable for the remaining seven input streams for memory based mode of operation. See the Register Address Space table in Register Space for the address offsets of the registers related to the remaining seven output streams. The registers ending with _0 are also mentioned in the register address space table. These registers are also applicable for stream mode.