Register Space - 1.1 English

The Video Scene Change Detection IP has specific registers that allow you to control the operation of the core. All registers have an initial value of zero. The following table provides a detailed description of all the registers that apply globally to the IP.

Table 1. Register Address Space
Address (hex) BASEADDR+	Register Name	Access Type	Register Description
0x0000	Control	R/W	Bit[0] = ap_start (R/W/COH) ¹ Bit[1] = ap_done (R/COR) ¹ Bit[2] = ap_idle (R) Bit[3] = ap_ready (R) Bit[5] = Flush pending AXI transactions (R/W) Bit[6] = Flush done (R) Bit[7] = auto_restart (R/W) Others = Reserved
0x0004	Global Interrupt Enable	R/W	Bit[0] = Global interrupt enable Others = Reserved
0x0008	IP Interrupt Enable	R/W	Bit[0] = Channel 0 (ap_done) Bit[1] = Channel 1 (ap_ready) Others = Reserved
0x000C	IP Interrupt Status Register	R/TOW ¹	Bit[0] = Channel 0 (ap_done) Bit[1] = Channel 1 (ap_ready) Others = Reserved
0x00010	Width 0	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x0018	Height 0	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x0020	Stride 0	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x0028	Video format 0	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x0030	Subsample 0	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x0038	Sad 0	R	Bit[31] to Bit[0] = Programmable Others = Reserved
0x0040	Frame buffer 0	R/W	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00110	Width 1	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00118	Height 1	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00120	Stride 1	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00128	Video format 1	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00130	Subsample 1	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00138	Sad 1	R	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00140	Frame buffer 1	R/W	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00210	Width 2	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00218	Height 2	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00220	Stride 2	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00228	Video format 2	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00230	Subsample 2	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00238	Sad 2	R	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00240	Frame buffer 2	R/W	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00310	Width 3	R/W	Bit[15] to Bit[0] = Programmable Others - Reserved
0x00318	Height 3	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00320	Stride 3	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00328	Video format 3	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00330	Subsample 3	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00338	Sad 3	R	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00340	Frame buffer 3	R/W	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00410	Width 4	R/W	Bit[15] to Bit[0] = Programmable Others - Reserved
0x00418	Height 4	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00420	Stride 4	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00428	Video format 4	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00430	Subsample 4	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00438	Sad 4	R	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00440	Frame buffer 4	R/W	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00510	Width 5	R/W	Bit[15] to Bit[0] = Programmable Others - Reserved
0x00518	Height 5	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00520	Stride 5	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00528	Video format 5	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00530	Subsample 5	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00538	Sad 5	R	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00540	Frame buffer 5	R/W	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00610	Width 6	R/W	Bit[15] to Bit[0] = Programmable Others - Reserved
0x00618	Height 6	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00620	Stride 6	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00628	Video format 6	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00630	Subsample 6	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00638	Sad 6	R	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00640	Frame buffer 6	R/W	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00710	Width 7	R/W	Bit[15] to Bit[0] = Programmable Others - Reserved
0x00718	Height 7	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00720	Stride 7	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00728	Video format 7	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00730	Subsample 7	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
0x00738	Sad 7	R	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00740	Frame buffer 7	R/W	Bit[31] to Bit[0] = Programmable Others = Reserved
0x00780	Stream enable	R/W	Bit[15] to Bit[0] = Programmable Others = Reserved
COR = Clear on Read, COH - Clear on Handshake, TOW = Toggle on Write Control Register (0x0000), Global Interrupt Enable Register (0x0004), IP Interrupt Enable Register (0x0008), and IP Interrupt Status Register (0x000C) are explained in section S_AXILITE Control Register Map of Vitis High-Level Synthesis User Guide (UG1399). These registers definitions can have some additional bits; however, in the current IP you are only accessing the bits mentioned in Table 10. Therefore, you only need to consider these bits while accessing the Control Register, Global Interrupt Enable Register, IP Interrupt Enable Register, and IP Interrupt Status Register.