The synthesizable design uses AMD Zynq™ UltraScale+™ MPSoC processor, AXI4 master, and PS DDR controller core to access DDR memory. The interrupt port of the Video Scene Change Detection IP is connected to Zynq UltraScale+ MPSoC. The IP sends interrupt signals after generating the SAD values for all input streams in memory based mode.
The synthesizable example design requires both Vivado and AMD Vitis™ tools.
The first step is to run synthesis, implementation, and bitstream generation in the Vivado tools. After completing these steps, select .
In the window, select Include bitstream. Select an export directory, and click OK.
The remaining work is performed in the AMD Vitis unified software platform. The Video Scene Change Detection IP example design application file is found in the following Vitis directory: <install_directory>/<release>/data/embeddedsw/XilinxProcessorIPLib/drivers/v_scenechange_v1_2/examples/