Detailed Pipeline Implementation - 1.0 English

DSP Macro LogiCORE IP Product Guide (PG323)

Document ID
PG323
Release Date
2021-01-25
Version
1.0 English
Figure 1. DSP Macro Detailed Implementation

The previous figure iillustrates the generalized DSP Macro implementation.

Note:
  • The second stage add/sub input mux implementations vary depending on the selected device.
  • A static mux is resolved at core generation, whereas a dynamic mux is implemented in the generated core.

Users requiring a specific mapping to registers in the DSP48 or DSP58 primitive can use the following table to determine the corresponding DSP Macro registers. See the Versal ACAP DSP Engine Architecture Manual (AM004), UltraScale Architecture DSP Slice User Guide (UG579), or the 7 Series DSP48E1 Slice User Guide (UG479).

Table 1. Register Mapping for DSP Macro
DSP Macro Using Pre-adder 1 No Pre-adder
D3 D N/A
A3 A1 A1
A4 AD A2
B3 B1 B1
B4 B2 B2
  1. The mapping of A4 changes depending on whether the pre-adder is used so the tiered latency model is maintained.